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CT1496-2 MIL-STD-1397 Type E 10MHz Low Level Serial Manchester 32 Bit Encoder
Features
* * * * * * * * * * Implements Type E protocol Operates with a single +5V supply Single clock input (40MHz) Selectable 4, 34, 35 bit operation Selectable Parity Includes parallel to serial converter Self-test outputs for BITE applications External encoder inhibit Bipolar Construction Use with CT1469-2 (transceiver) & CT1508-2 (4 bit decoder) to provide a complete low level serial interface
CIRCUIT TECHNOLOGY
www.aeroflex.com
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General Description
CT1496-2 is a hybrid microcircuit which incorporates a low level serial Manchester encoder in a single package. The encoder accepts 32 bit parallel data and outputs a 35 bit Manchester encoded TTL NRZ serial stream (34 bit transmission if parity option is not selected). Preceding the 32 data bits are a synchronization and word identifier bit and a parity bit trails the data (parity is optional and may be disabled). A self-test feature is implementd allowing the user to verify transmit patterns. Aeroflex Circuit Technology is a 80,000 square foot MIL-PRF-38534 certified facility in Plainview, N.Y.
Sync Bit LSB 32-Bit Word Register MSB Sys Clr / Load Sync Data C/I Bit4 Vcc Timing Section TX Data TX Data Data ST Data ST WI Bit External Encoder Inhibit
32-Bit Parallel Word Input
2-Bit Register
Mux
Manchester Encoder
DeMux
SIS/SOS Input +5V Parity Select Encoder Enable Transmit / Self-Test 4-Bit SIS/SOS Select 34-Bit Select 35-Bit Select 40MHz Clock TTL GND
4-Bit Register
Controller
Parity Generator
TX Inhibit
Block Diagram eroflex Circuit Technology - Data Bus Modules For The Future (c) SCDCT1496 REV A 3/22/00
Aeroflex Circuit Technology 2 SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
40MHz Parallel Input Data (DBN) Bit 1 Bit 2 Bit 3
OUTPUT LOGIC STATE TRUTH TABLE CONDITIONS OUTPUT STATES TX INH (29) TX/ST (37) DATA (39) DATA (38) DATAst (33) DATAst (32) LOW LOW HIGH LOW HIGH LOW HIGH HIGH HIGH HIGH (DBn) HIGH HIGH HIGH (DBn) LOW LOW (DBn) LOW LOW LOW (DBn) LOW
Bit 3 System Clear / Load Encoder Enable TX Inhibit Transmit / Self Test DATA DATA DATAst DATAst
T1 T2 PW1 T3 PW2 T4
HIGH
T5 T6 T7 PW3 T8 T9 PW5 Output Data Bit 1 Example =1 Output Data Bit 2 Example =1 Output Data Bit 3 Example =0 PW6 PW4
T11 T10 T10 T10 T10 Output Data Bit N Example =1
Figure 1 - Encoder Timing Waveforms
Absolute Maximum Ratings
Parameter
Supply Voltage 1/ Logic Input Voltage Logic Input Current Power Dissipation 2/ Storage Temperature Range Operating Case Temperature Range
Rating
+7.0 -1.2 to +5.5 -10 (low logic) 3.25 -65 to +125 -55 to +100
Units
V V mA W C C
1/ Power sequencing shall not be required. 2/ For Logic output short circuits, line to ground logic outputs shall withstand currents not exceeding 100mA for one second for one output at a time.
DC Electrical Characteristics
(VDD = 5V 10%, TC = -55 C to +100C, unless otherwise specified)
SYMBOL PARAMETER LIMIT
DATA 1/, DATA 1/, DATAst 2/ & DATAst 2/ VOH VOL TX INHIBIT VOH VOL Logic High Output Voltage 3/, 4/ Logic Low Output Voltage 4/ 2.5V min @ IOH = -150A 0.5V max @ IOL = 5mA Logic High Output Voltage 3/, 4/ Logic Low Output Voltage 4/ 2.5V min @ IOH = -50A 0.5V max @ IOL = 2mA
40MHz, Encoder Enable & External Encoder Inhibit IIH IIL Logic High Input Current Logic Low Input Current 3/ 100A max @ VIH = 2.5V -4mA max @ VIL = 0.5V
Parity Select, 34 Bit Select, 35 Bit Select & Sys Clear / Load IIH IIL Logic High Input Current Logic Low Input Current 3/ 50A max @ VIH = 2.5V -2mA max @ VIL = 0.5V
Transmit / Self Test & 4 Bit SIS / SOS Select IIH IIL Logic High Input Current Logic Low Input Current 3/ 150A max @ VIH = 2.5V -6mA max @ VIL = 0.5V
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
DC Electrical Characteristics (con't)
(VDD = 5V 10%, TC = -55 C to +100C, unless otherwise specified)
SYMBOL PARAMETER LIMIT
Sync Bit, WI Bit, 4 Bit SIS / SOS Input & 32 Bit Parallel Word Input IIH IIL Logic High Input Current Logic Low Input Current 3/ 20A max @ VIH = 2.5V -400A max @ VIL = 0.5V
DC Supply Currents ICC VCC = +5.5V (pin 31), all other pins at GND 590mA max
Notes: 1/ and 2/ The total loads on these outputpairs (1 & 2) must be matched to within 15pF in order to maintain signal skews between the lines of < 5nSec maximum. 3/ Current out of a terminal is given as a negative value. 4/ Maximum total capacitance loads allowable on these pins are: DATA, DATA TX INHIBIT DATAst & DATAst 40 pF max 45 pF max 50 pF max
AC Electrical Characteristics
(VCC = 5V 10%, TC = -55 C to +100C, See Figure 1, unless otherwise specified)
Symbol
T1 T2 PW1 T3 PW2 T4 T5 T6 T7 PW3 PW4 T8 T9 PW5 PW6 T10 T11
Parameter / Condition
Stable input data setup time prior to Sys Clr / Load rising edge Stable input data hold time after Sys Clr / Load rising edge Sys Clr / Load pulsewidth Sys Clr / Load disable to Encoder Enable pulse Encoder Enable pulsewidth Encoder Enable rising edge to TX Inhibit disable (thruput delay) Transmit / Self Test selection to TX Inhibit disable set-up time TX Inhibit disable to output data delay (Transmit / Self Test = high) DATA Output to DATA output delay {ZLOAD (DATA) = ZLOAD (DATA), CLOAD < 40pF} DATA and DATA output half-bit pulsewidth DATA and DATA output bit pulsewidth TX Inhibit disable to output DATAST delay DATAST output DATAST output delay {ZLOAD (DATAST) = ZLOAD (DATAST), CLOAD < 50pF} DATAST and DATAST output half-bit pulsewidth DATAST and DATAST output bit pulsewidth End of output DATA, DATA, DATAst or DATAst to TX Inhibit enable TX Inhibit enable to next Transmit / Self Test selection
4
Min
40 20 50 40 100 30 50 47 97 47 97 50
Max
400 140 10 5 53 103 10 5 53 103 10 -
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
Input Capacitance Table
Pin #
41 40 34 20 22 21 42 37 36 15 16 24 - 27 43 - 60, 1 - 14
Pin Name
40 MHz Encoder Enable External Encoder Inhibit Parity Select 34 Bit Select 35 Bit Select Sys Clr / Load Transmit / Self Test 4 Bit SIS / SOS Select WI Bit Sync Bit 4 Bit SIS / SOS Input 32 Bit Parallel Word Input
Maximum Input Capacitance
30 pF 30 pF 30 pF 15 pF 15 pF 15 pF 15 pF 45 pF 45 pF 15 pF 15 pF 15 pF 15 pF
Word Selection Truth Table
4 Bit Select
High Low Low Low
34 Bit Select
X High Low Low
35 Bit Select
X X High Low
Word Length
4 Bit 34 Bit 35 Bit Illegal
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
Functional Description and Pinout
Pin # 31 39 38 29 33 Pin Name VCC DATA 1/ DATA 1/ TX Inhibit DATAST 1/ +5V 10% Manchester Encoder Serial DATA Output (Max Load 40 pF). Manchester Encoded Serial DATA Output (Max Load 40 pF). Transmit Inhibit Output (Max load 45 pF). Manchester Encoded Serial DATA Output for purpose of self-testing. Connected to decoder self-test input. Controlled by Transmit / Self-Test function (max load 50 pF). Manchester Encoded Serial DATA Output for Purpose Of Self-Testing. Connected to Decoder Self-test Input. Controlled By Transmit / Self-Test Function. (Max Load 50 pF). 40 MHz 0.1% TTL input to encoder. Symmetry 35% min. Rise and fall times 5nSec max. Low Level Input for even parity, high level input for odd parity. Parity determined on 34 Bit word (Sync, W1, 32 Data Bits). Asynchronous enable input pulse. Enables transmission when a high level signal is input. High level input enables transmission of data thru data and data outputs: Disables DATAst and DATAst outputs; Which both go to low logic state. Low level input enables transmission of DATA thru DATAst and DATAst outputs; Disables DATA and DATA outputs, which both go to high logic state. High level selects 4 Bit SIS/SOS transmission. This will enable 4 Bit inputs to be loaded into the 4 Bit SIS / SOS register High level selects 34 Bit transmission (32 Data Bits, W1 Bit and Sync Bit). High level selects 35 Bit transmission (32 data Bits, W1 Bit, Sync Bit and Parity Bit). A low level allows data at input pins to be loaded, clears the parity generator and initializes the internal controller. A positive going edge latches input data present at that time into the data registers. Function
32
DATAST 1/
41 20
40 MHz Parity Select
40 37
Encoder Enable Transmit / Self-Test
36
4 Bit SIS / SOS Select
22 21 42
34 Bit Select 35 Bit Select Sys Clr / Load
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
Functional Description and Pinout (con't)
Pin # 43-60 1-14 Pin Name 32 Bit Parallel Word Input (Pin 43 MSB) (Pin 14 LBS) Sync Bit Function 32 Bit Parallel Input for Data Word. This data is latched into the 32 Bit register on a Sys Clr / Load positive going edge.
16
Input for Sync Bit which is latched into the 2 Bit Register on a Sys Clr/Load positive going edge (Sync Bit always logic high). Input for Word Identifier Bit Which is latched into the 2 Bit register on a Sys Clr / Load positive going edge. 4 Bit Parallel Input for SIS / SOS which is latched into the 4 Bit SIS/SOS Register on a Sys Clr / Load positive going edge.
15
WI Bit 4 Bit SIS / SOS Input: Bit 4 (MSB) C/I Data Sync (LSB) External Encoder Inhibit
24 25 26 27 34
Asynchronous inhibit. A low forces DATA and DATA to a common high state and DATAST and DATAst to a common low state. Grounds. All ground pins are common and connected to hybrid case.
17 18 19 23 28 30 35 1/
Equal loads must be applied to these output pairs.
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
Pin #'s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Functions (BIT 14) (BIT 13) (BIT 12) (BIT 11) (BIT 10) (BIT 9) (BIT 8) (BIT 7) (BIT 6) (BIT 5) (BIT 4) (BIT 3) (BIT 2) (BIT 1) LSB W.I. BIT SYNC BIT GND GND GND PARITY SELECT 35 BIT SELECT 34 BIT SELECT GND BIT 4 (MSB) CLEAR/LOAD DATA SYNC (LSB) GND TX INHIBIT GND
Pin #'s 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Functions Vcc (+5V) DATA ST DATA ST EXTERNAL ENCODER INHIBIT GND 4 BIT SIS/SOS SELECT TX/SELF TEST SERIAL DATA SERIAL DATA ENCODER ENABLE 40MHz IN SYS CLR/LOAD (BIT 32) MSB (BIT 31) (BIT 30) (BIT 29) (BIT 28) (BIT 27) (BIT 26) (BIT 25) (BIT 24) (BIT 23) (BIT 22) (BIT 21) (BIT 20) (BIT 19) (BIT 18) (BIT 17) (BIT 16) (BIT 15)
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SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number CT1496-2 Package Flat Package
Flat Package Outline
1.590 MAX 1.450
(30 Leads/Side on .050 centers)
.175 MAX
1.015 MAX Lead 1 & ESD Designator
.450 MIN .015 .003 .050 TYP
.010 .002
Specifications subject to change without notice.
Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803
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Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800)THE-1553
SCDCT1496 REV A 3/22/00 Plainview NY (516) 694-6700

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